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HV528
16-Channel Serial to Parallel Converter with High Voltage Backplane Driver and Push-Pull Outputs
Features
HVCMOS(R) technology Output voltage up to +200V Shift register speed 500kHz @ VDD = 1.7V 16 high voltage outputs High voltage backplane driver CMOS input levels
General Description
The HV528 is a 200V, 16-channel serial to parallel converter. The high voltage outputs and the backplane driver are designed to source and sink 1.0mA. The high voltage outputs are controlled by a 16-bit serial shift register, followed by a 16-bit latch. Data is shifted through the shift registers during the low to high clock transition. A data output buffer is provided for cascading multiple devices. Data is transferred to the 16-bit latch when a logic level low is applied to the LE input. Data is stored in the latch when LE is high. Output states are controlled by the data in the latch and by the POL pin.
Applications
Multiple segment EL display Piezoelectric transducer driver Braille driver
Typical Application Circuit
Low Voltage Power Supply High Voltage VBIAS Power Supply
DIN
HVOUT1
CLK
Low Voltage
16
High Voltage
EL Segment Panel
Micro Processor
LE
POL DOUT
Shift Register Latches
Level Translators & Push-Pull Output
HVOUT16
BP
Supertex HV528
to DIN of another HV528 for cascading (if needed)
HV528
Ordering Information
Package Option Device 32-Lead QFN
5x5mm body, 1.0mm height (max), 0.50mm pitch
1
Pin Configuration
32
HV528
HV528K6-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter Logic supply, VDD High voltage supply, VPP Translator supply voltage, VBIAS Logic input levels Operating junction temperature Storage temperature range Value -0.5V to 7.0V 215V -0.5V to 7.0V -0.5V to VDD +0.5V -40C to +125C -65C to +150C
32-Lead QFN (K6)
(top view) (Bottom side exposed center pad is at VPP potential)
Product Marking
HV528 LLLLLL YYWW AAACCC
L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
32-Lead QFN (K6)
Operating Supply Voltages and Conditions
Sym VDD VBIAS VPP VIH VIL TA Parameter Logic supply voltage Level translator supply voltage Positive high voltage supply High-level input voltage Low-level input voltage Operating temperature Min 1.7 5.4 50 0.9VDD 0 0 Typ 3.0 +70 Max 5.5 6.6 200 VDD Units V V V V V C Conditions -------------
Notes: 1. External ground noise reduction circuit will be provided by design upon characterization. Power-up sequence should be the following*: 1. Apply ground 2. Apply VDD 3. Set all inputs (DIN, CLK, LE , POL) to a known state 4. Apply VBIAS 5. Apply VPP Power-down sequence should be the reverse of the above *This power up sequence requires an external high voltage diode between VDD and VPP. Without the diode, power up VPP to a VDD level first to bias the silicon substrate. After all other signals are powered, finish raising the VPP to its final level.
2
HV528
DC Electrical Characteristics
Sym IDD IDDQ IBIAS IBIASQ IPPQ IIH IIL VOH Parameter VDD supply current Quiescent VDD supply current VBIAS supply current Quiescent VBIAS current Quiescent VPP supply current High-level logic input current Low-level logic input current HVOUT & BP DOUT VOL CDIN CDOUT Low level output HVOUT & BP DOUT
(Over operating supply voltages and temperature, unless otherwise noted)
Min VPP -30V VPP -16V VDD -1.0V -
Typ -
Max 1.0 10 100 10 100 10 -10 6.0 1.0 10 10
Units mA A A A A A A V V V V V pF pF
Conditions fCLK = 500kHz All logic inputs = VDD or 0V All HVOUTS switching at 1.0kHz. Peak IBIAS = 200mA with all channels switching No HVOUT switching VPP = 200V, outputs are static VIH = VDD VIL = 0V IHVOUT = -1.0mA, 50V VPP 100V IHVOUT = -1.0mA, 100V < VPP 200V IDOUT = -1.0mA IHVOUT = 1.0mA IDOUT = 1.0mA -----
High level output
Logic input capacitance Logic output capacitance
AC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted)
Sym fCLK tC tSU tH tCLE tWLE tDD tPHV tOR tOF tOC Parameter Clock frequency Clock high / low pulse width Data setup time before clock rises Data hold time after clock rises LE from CLK setup time LE pulse width Clock negative edge to DOUT delay Delay time from inputs for HVOUT / BP to start rise/fall HVOUTPUT / BP rise time HVOUTPUT / BP fall time Width of POL pulses Min 0 1.0 50 50 15 100 tPHV + tOR/tOF Typ Max 500 150 500 300 300 Units kHz s ns ns ns ns ns ns s s s Conditions ------------CLDOUT = 50pF, (CLDOUT includes CDIN and CDOUT) VPP = 200V, VBIAS = 5.4V CL = 1500pF, VPP = 200V CL = 1500pF, VBIAS = 5.4V, VPP = 200V ---
3
HV528
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out VBIAS
HVOUT
GND
GND HVGND
Logic Inputs
Logic Data Output
High Voltage Outputs
VBIAS SUPPLY
The VBIAS supply operates from 5.4 to 6.6V. It is the gate drive voltage for all of the output N-channel MOSFETs. This allows the output peak current sink to be set by varying the VBIAS voltage. A higher VBIAS voltage will increase the current sinking capability. The operating VDD range is 1.7 to 5.5V. A plot showing the typical characteristics of ISINK vs VBIAS is shown below.
Typical HVOUT ISINK vs VBIAS
(VPP = 200V, CLOAD = 1.0nF)
20
18
ISINK (mA)
16
14
12
10 5.0
5.5
6.0
6.5
VBIAS (V)
4
HV528
Switching Waveforms
5
HV528
Functional Block Diagram
VDD
DIN
Logic
Level Translator
HVOUT1
CLK 16-bit Shift Register
GND
HVGND
16-bit Latch Level Translator
Logic
HVOUT16 HVGND
DOUT
GND HVGND
GND LE POL Level Translator & Buffer HVGND BP
Function Table
Inputs Function DIN H OR L X X X Store data in latches X L H X X CLK L L X X X X LE H L L H H L L H H POL X H L H L H H L H Shift Reg 1 2...16 H or L * * L H ... * * L H Outputs HV Outputs 1 2...16 ... *..........* *..........* (b) ... ... (b) ... ... ... (b) ... BP X L H L H L L H L DOUT X X
Load S/R Transfer data in latch
*..........* *..........* ... ... ... ... ... ...
Transparent mode
Invert mode
Notes: H = high level, L = low level, X = irrelevant, = low-to-high transition = dependent on previous stage's state before the last CLK or last LE low * = data at the last CLK (b) = bar over all symbols
6
HV528
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 NC VPP GND NC DIN NC CLK VDD POL LE NC DOUT NC VBIAS HVGND BP HVOUT16 HVOUT15 HVOUT14 HVOUT13 Center Pad Description High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output No connect High voltage supply Logic ground No connect Data in No connect Clock input logic Logic supply voltage Polarity bar input logic Latch enable bar input logic No connect Data out No connect Level translator bias voltage High voltage ground High voltage backplane output High voltage push-pull output High voltage push-pull output High voltage push-pull output High voltage push-pull output The center pad is at VPP potential. Leave floating or connect to VPP. Do not ground.
7
HV528
32-Lead QFN Package Outline (K6)
5x5mm body, 1.0mm height (max), 0.50mm pitch
32 D D2 32 Note 1 (Index Area D/2 x E/2) 1 Note 1 (Index Area D/2 x E/2) E b e
1
E2
View B
Top View
Bottom View
Note 3
A A3 A1
Seating Plane L1 Note 2
L
Side View
View B
Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.
Symbol MIN Dimension (mm) NOM MAX
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 4.85 5.00 5.15
D2 1.05 3.45
E 4.85 5.00 5.15
E2 1.05 3.45
e 0.50 BSC
L 0.45 0.50 0.55
L1 0.00 0.15
0O 14O
JEDEC Registration MO-220, Variation VHHD-6, Issue K, June 2006. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www. supertex.com/packaging.html.)
Doc.# DSFP-HV528 NR042808 8

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